1. Field of the Invention
The present invention relates to a method for fabricating semiconductor integrated circuits, and more specifically to a method for fabricating trench isolations with high aspect ratio.
2. Description of the Related Art
Recently, as fabrication techniques for semiconductor integrated circuits have developed, the number of elements in a chip has increased. Element size has integration density has increased. Fabrication line width has decreased from sub-micron to quarter-micron, and smaller. Regardless of the reduction in element size, however, adequate insulation or isolation must be is required among individual elements in a chip so that optimal performance can be achieved. This technique is called device isolation technology. The main object is to form isolations among individual elements, reducing their size as much as possible, ensuring superior isolation while creating more chip space for more elements.
Among the different element isolation techniques LOCOS and trench isolation are the most commonly used. The trench isolation technique has received particular notice as it provides a small isolation region and the substrate surface remains level post process. The conventional high density plasma chemical vapor deposition (HDPCVD) method for fabricating trench isolations with high aspect ratio, in excess of 6, for example, requires multiple deposition and etching cycles, thus it is expensive and offers reduced yield. Additionally, as the density of integrated circuits increases and element size is reduced, HPCVD provides inadequate step coverage resulting in incompletely filled trenches, and is detrimental to isolation between elements.
Currently, the low pressure chemical vapor deposition (LPCVD) method is typically employed to step coverage. To further illustrate the process, FIGS. 1A to 1B show the fabrication method in cross sections.
First, referring to FIG. 1A, a pad layer is formed on a semiconductor substrate 10. For example, a pad oxide layer 11 is formed on a silicon substrate by CVD or thermal oxidation, and a pad nitride layer 12 is deposited on the pad oxide layer 11 by CVD. The pad oxide layer 11 and the pad nitride layer 12 comprise the pad layer. Next, the pad oxide layer 11 and the pad nitride layer 12 are patterned by photolithography and etching to expose the area of the semiconductor substrate 10 where the element isolation region is to be formed. The patterned pad layer is subsequently used as a mask to etch the semiconductor substrate 10, and a trench is formed therein for the element isolation region.
Next, referring to FIG. 1B, thermal oxidation is performed to grow an oxide liner 14 covering the bottom and sidewalls of the trench. Subsequently, a nitride liner 16 is formed conformally on the pad layer and the oxide liner 14. LPCVD is then performed, for example, using TEOS as the reactant to deposit a TEOS layer 18 as a dielectric layer, completely filling the trench shown in FIG. 1B. Although LPCVD can improve step it has some drawbacks as shown in FIG. 1C.
Referring to FIG. 1C, as the aspect ratio of the trench exceeds 6, the conventionally deposited (by LPCVD) TEOS layer 18, may have voids 20 near the opening of the trench. The voids 20 are then filled with etching solution, thus the TEOS layer 18 is etched and larger void formations are created therein. Larger voids result in structural instability and reduced element reliability. Additionally, to improve the inferior TEOS dielectric characteristics it is necessary to perform a high temperature thermal annealing procedure with longer reaction time. The intensive thermal annealing procedure, however, often adversely affects the peripheral elements.